A novel method to characterize CMOS process fluctuations in subthreshold current mirrors （SCM） is reported. The proposed model is succinct in methodology and calculation complexity compared with previous statistical models. However,it provides favorable estimations of CMOS process fluctuations on the SCM circuit, which makes it promising for engineering applications. The model statistically abstracts physical parameters, which depend on the IC process, into random variables with certain mean values and standard deviations, while aggregating all the random impacts into a discrete martingale. The correctness of the proposed method is experimentally verified on an SCM circuit implemented in an SMIC 0.18μm CMOS 1P6M mixed signal process with a conversion factor of 100 in an input range from 100pA to lμA. The pro- posed theory successfully predicts - 10% of die-to-die fluctuation measured in the experiment, and also suggests the -lmV of threshold voltage standard deviation over a single die,which meets the process parameters suggested by the design kit from the foundry. The deviations between calculated probabilities and measured data are less than 8%. Meanwhile, pertinent suggestions concerning high fluctuation tolerance subthreshold analog circuit design are also made and discussed.
A fully integrated CMOS bio-chip is designed in a SMIC 0.18μm CMOS mixed signal process and successfully integrated with a novel bio-nano-system. The proposed circuit integrates an array of 4 × 4 （16 pixels） of 19μm × 19μm electrodes,a counter electrode, a current mode preamplifier circuit （CMPA） ,a digital decoding circuit,and control logics on a single chip, It provides a - 1.6- 1.6V range of assembly voltage,Sbit potential resolution, and a current gain of 39.8dB with supply voltage of 1.8V. The offset and noise are smaller than 5.9nA and 25.3pArms,respectively. Experimental resuits from on-chip selective assembly of 30nm poly （ethylene glycol） （PEG） coated magnetic nano-particles （MNPs） targeted at biosensor applications are included and discussed to verify the feasibility of the proposed circuits.
